rev. 1.7 july 2009 www.aosmd.com page 1 of 9 AOZ8002 ultra-low capacitanc e tvs diode array general description the AOZ8002 is a transient voltage suppressor array designed to protect high speed data lines from esd and lightning. this device incorporates eight surge rated, low capaci- tance steering diodes and a tvs in a single package. during transient conditions, the steering diodes direct the transient to either the positive side of the power supply line or to ground. they may be used to meet the esd immunity requirements of iec 61000-4-2, level 4. the tvs diodes provide effective suppression of esd voltages: 15kv (air discharge) and 8kv (contact discharge). the AOZ8002 comes in a dfn-6 1.6mm x 1.6mm pack- age and is rated over a -40c to +85c ambient tempera- ture range. the AOZ8002 is compatible with both lead free and snpb assembly techniques. the small size, low capacitance and high esd pr otection makes it ideal for protecting high speed video and data communication interfaces. features esd protection for high-speed data lines: ? iec 61000-4-2, level 4 (esd) immunity test ? 15kv (air discharge) and 8kv (contact discharge) ? iec 61000-4-5 (lightning) 5a (8/20s) ? human body model (hbm) 15kv small package saves board space low insertion loss protects four i/o lines low capacitance between i/o lines: 0.9pf low clamping voltage low operating voltage: 5.0v pb-free device halogen free applications usb 2.0 power and data line protection video graphics cards monitors and flat panel displays digital video interface (dvi) 10/100/1000 ethernet notebook computers typical application figure 1. 2 usb high speed ports +5v r t vbus AOZ8002 usb host controller downstream ports vbus d+ d- gnd r t +5v r t vbus d+ d- gnd r t
AOZ8002 rev. 1.7 july 2009 www.aosmd.com page 2 of 9 ordering information aos green products use reduced levels of halogens, and are also rohs compliant. please visit www.aosmd.com/web/quality/rohs_compliant.jsp for additional information. pin configuration absolute maximum ratings exceeding the absolute maximum ratings may damage the device. notes: 1. iec 61000-4-2 discharge with c discharge = 150pf, r discharge = 330 ? . 2. human body discharge per mil-std-883, method 3015 c discharge = 100pf, r discharge = 1.5k ? . maximum operating ratings part number ambient temperature range package environmental AOZ8002dil -40c to +85c 1.6mm x 1.6mm dfn-6 rohs compliant green product 1 2 3 6 5 4 ch1 vn ch2 ch4 vp ch3 dfn-6 (top view) parameter rating vp ? vn 6v peak pulse current (i pp ), t p = 8/20s 5a storage temperature (t s ) -65c to +150c esd rating per iec61000-4-2, contact (1) 8kv esd rating per iec61000-4-2, air (1) 15kv esd rating per human body model (2) 15kv parameter rating junction temperature (t j ) -40c to +85c
AOZ8002 rev. 1.7 july 2009 www.aosmd.com page 3 of 9 electrical characteristics t a = 25c unless otherwise specified. specifications in bold indicate a temperature range of -40c to +85c. notes: 3. these specifications are guaranteed by design. 4. the working peak reverse voltage, v rwm , should be equal to or greater than the dc or continuous peak operating voltage level. 5. v br is measured at the pulse test current i t . 6. measurements performed wi th no external capacitor on v p (pin 5 floating). 7. measurements performed with v p biased to 3.3 volts (pin 5 @ 3.3v). 8. measurements performed using a 100ns transmission line pulse (tlp) system. symbol parameter conditions min. typ. max. units v rwm reverse working voltage between pin 5 and 2 (4) 5.5 v v br reverse breakdown voltage i t = 1ma, between pins 5 and 2 (5) 6.6 v i r reverse leakage current v rwm = 5v, between pins 5 and 2 1.0 a v f diode forward voltage i f = 15ma 0.70 0.85 1 v v cl channel clamp voltage positive transients negative transient i pp = 1a, tp = 100ns, any i/o pin to ground (3)(6)(8) 10.00 -2.00 v v channel clamp voltage positive transients negative transient i pp = 5a, tp = 100ns, any i/o pin to ground (3)(6)(8) 12.00 -3.00 v v channel clamp voltage positive transients negative transient i pp = 12a, tp = 100ns, any i/o pin to ground (3)(6)(8) 14.00 -5.00 v v c j junction capacitance v r = 0v, f = 1mhz, any i/o pin to ground (3)(6) 1.85 1.94 pf v r = 0v, f = 1mhz, between i/o pins (3)(6) 0.9 0.94 pf v r = 0v, f = 1mhz, any i/o pin to ground (3)(7) 1.0 1.17 pf c j channel input capacitance matching v r = 0v, f = 1mhz, between i/o pins (3)(6) 0.03 pf
AOZ8002 rev. 1.7 july 2009 www.aosmd.com page 4 of 9 typical performance characteristics typical variation of c in vs v r (f = 1mhz, t = 25c) 1.30 1.20 1.10 1.00 0.90 0.80 0.70 0.60 0.00 1.00 2.00 vp (pin 5) = 3.3v 3.00 4.00 5.00 input voltage (v) input capacitance (pf) clamping voltage vs. peak pulse current (tperiod = 100ns, tr = 1ns) 14 13 12 11 10 9 8 7 6 peak pulse current, i pp (a) clamping voltage, v cl (v) 0 2 4 6 8 10 12 forward voltage vs. forward current (tperiod = 100ns, tr = 1ns) 7 6 5 4 3 2 1 0 forward current (a) forward voltage (v) 0 2 4 6 8 10 12 i/o ? gnd insertion loss (s21) vs. frequency (vp = 3.3v) 1 0 -1 -2 -3 -4 -5 -6 -7 -8 -9 -10 frequency (mhz) insertion loss (db) 100 10 1000 analog crosstalk (i/o?i/o) vs. frequency 20 0 -20 -40 -60 -80 frequency (mhz) insertion loss (db) 1 10 100 1,000 10,000 esd clamping 8kv contact per iec61000-4-2 note: data was taken with a 10x attenuator
AOZ8002 rev. 1.7 july 2009 www.aosmd.com page 5 of 9 application information the AOZ8002 tvs is design to protect four data lines from fast damaging transient over-voltage by clamping it to a reference. when the tr ansient on a protected data line exceed the reference voltage the steering diode is forward bias thus, conducting the harmful esd transient away from the sensitive circuitry under protection. pcb layout guidelines printed circuit board layout is the key to achieving the highest level of surge immunity on power and data lines. the location of the protection devices on the pcb is the simplest and most important design rule to follow. the AOZ8002 devices should be lo cated as close as possible to the noise source. the placement of the AOZ8002 devices should be used on all data and power lines that enter or exit the pcb at th e i/o connector. in most systems, surge pulses occur on data and power lines that enter the pcb through the i/o connector. placing the AOZ8002 devices as clos e as possible to the noise source ensures that a sur ge voltage will be clamped before the pulse can be coupled into adjacent pcb traces. in addition, the pcb should use the shortest possible traces. a short trace length equates to low impedance, which ensures t hat the surge energy will be dissipated by the AOZ8002 device. long signal traces will act as antennas to receive energy from fields that are produced by the esd pulse. by keeping line lengths as short as possible, the efficien cy of the line to act as an antenna for esd related fiel ds is reduced. minimize interconnecting line lengths by placing devices with the most interconnect as close together as possible. the protection circuits should shunt the surge voltage to either the reference or chassis ground. shunting the surge voltage directly to the ic?s signal ground can cause ground bounce. the clamping performance of tvs diodes on a single ground pcb can be improved by minimizing the impedance with relatively short and wide ground traces. the pcb layout and ic package parasitic inductances can cause significant overshoot to the tvs?s clamping voltage. the in ductance of the pcb can be reduced by using short trace lengths and multiple layers with separate ground and powe r planes. one effective method to minimize loop problems is to incorporate a ground plane in the pcb design. the AOZ8002 ultra-low capacitance tvs is designed to protect four high speed data transmission lines from transient over-voltages by clamping them to a fixed reference. the low inductance and construction minimizes voltage overshoot during high current surges. when the voltage on the protected line exceeds the reference voltage the internal steering diodes are forward biased, conducting the transient current away from the sensitive circuitry. good circuit board layout is critical for the suppression of esd induced transients. the following guidelines are recommended: 1. place the tvs near the io terminals or connectors to restrict transient coupling. 2. fill unused portions of the pcb with ground plane. 3. minimize the path length between the tvs and the protected line. 4. minimize all conductive loops including power and ground loops. 5. the esd transient return path to ground should be kept as short as possible. 6. never run critical signals near board edges. 7. use ground planes whenever possible. 8. avoid running critical si gnal traces (clocks, resets, etc.) near pcb edges. 9. separate chassis ground traces from components and signal traces by at least 4mm. 10. keep the chassis ground trace length-to-width ratio <5:1 to minimize inductance. 11. protect all external connections with tvs diodes.
AOZ8002 rev. 1.7 july 2009 www.aosmd.com page 6 of 9 sim card port connection ieee1394 port connection sim 10/100 ethernet port connection AOZ8002 vcc reset clock i/o gnd AOZ8002 AOZ8002 AOZ8002 ieee 1394 phy ethernet controller ieee 1394 connector rj45 connector 56 1 270p 56 56 56 5.1k tpbiasx tpax+ tpax- tpbx+ tpbx- gnd trd0+ trd0- trd1+ trd1- trd2+ trd2- trd3- trd3+
AOZ8002 rev. 1.7 july 2009 www.aosmd.com page 7 of 9 package dimensions, dfn 1.6mm x 1.6mm e pin 1 id d b e1 d1 l e e1 r pin 1 id 1 6 a1 c a notes: 1. dimensions and tolerancing conform to asme y14.5m-1994. 2. all dimensions are in millimeters. symbols a a1 b c d d1 e e1 e e1 l r dimensions in millimeters side view top view bottom view min. 0.50 0.00 0.22 1.55 0.95 1.55 0.55 0.225 nom. 0.55 0.02 0.25 1.52 ref. 1.60 1.00 1.60 0.60 0.50 bsc 1.0 ref 0.275 0.20 max. 0.60 0.05 0.28 1.65 1.05 1.65 0.65 0.325
AOZ8002 rev. 1.7 july 2009 www.aosmd.com page 8 of 9 tape and reel dimensions, dfn 1.6mm x 1.6mm carrier tape reel leader / trailer & orientation tape size 8mm reel size ?149 m ?179.0 0.50 package dfn 1.6x1.6 a0 1.80 0.05 b0 1.80 0.05 k0 0.69 0.05 d0 1.55 0.05 d1 0.080 0.05 e 8.00 0.10 e1 1.75 0.10 e2 3.50 0.05 p0 4.00 0.10 p1 4.00 0.10 p2 2.00 0.10 t 0.20 0.05 n 55.0 0.50 trailer tape 300mm min. components tape orientation in pocket leader tape 500mm min. p1 p0 w1 n m h s k unit: mm unit: mm a0 b0 ref. 3 t k0 p2 e e2 e1 d0 d1 feeding direction w1 8.4 +1.5/-0.0 h 13.0 +0.50/-0.0 s 1.5 min. k 10.1 min. r 2.7 0.20
AOZ8002 rev. 1.7 july 2009 www.aosmd.com page 9 of 9 part marking pwl AOZ8002dil (1.6 x 1.6 dfn) assembly lot code product number code underscore denotes green product week code as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provid ed in the labeling, can be reasonably expected to result in a significant injury of the user. 2. a critical component in any component of a life support, device, or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. alpha & omega semiconductor reserves the right to make changes to this data sheet at any time without notice. life support policy alpha & omega semiconductor products ar e not authorized for use as critical components in life supp ort devices or systems.
|
